Messages in this thread | | | From | Mike Turquette <> | Date | Tue, 27 Nov 2012 10:15:52 -0800 | Subject | Re: [PATCH 2/6 v5] clk, highbank: Prevent glitches in non-bypass reset mode |
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On Tue, Nov 27, 2012 at 7:04 AM, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote: > > The highbank clock will glitch with the current code if the > clock rate is reset without relocking the PLL. Program the PLL > correctly to prevent glitches. > > Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> > Signed-off-by: Rob Herring <rob.herring@calxeda.com> > Cc: mturquette@linaro.org
Acked-by: Mike Turquette <mturquette@linaro.org>
Regards, Mike
> --- > Changes from v4 > None. > Changes from v3 > Changelog text and patch name now correspond to the actual patch. > was clk, highbank: remove non-bypass reset mode. > Changes from v2 > None. > Changes from v1: > Removed erroneous reformating. > > drivers/clk/clk-highbank.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c > index 52fecad..3a0b723 100644 > --- a/drivers/clk/clk-highbank.c > +++ b/drivers/clk/clk-highbank.c > @@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, > reg |= HB_PLL_EXT_ENA; > reg &= ~HB_PLL_EXT_BYPASS; > } else { > + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); > reg &= ~HB_PLL_DIVQ_MASK; > reg |= divq << HB_PLL_DIVQ_SHIFT; > + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); > } > writel(reg, hbclk->reg); > > -- > 1.7.11.7 >
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