| From | Mark Langsdorf <> | Subject | [PATCH 2/6 v2] clk, highbank: remove non-bypass reset mode | Date | Fri, 2 Nov 2012 13:51:45 -0500 |
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The highbank clock will glitch if the clock rate is reset without relocking the PLL. Remove the option to attempt reseting without relocking.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: mturquette@linaro.org
Changes from v2: Removed erroneous reformating.
--- drivers/clk/clk-highbank.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 52fecad..3a0b723 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, reg |= HB_PLL_EXT_ENA; reg &= ~HB_PLL_EXT_BYPASS; } else { + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg &= ~HB_PLL_DIVQ_MASK; reg |= divq << HB_PLL_DIVQ_SHIFT; + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); } writel(reg, hbclk->reg); -- 1.7.11.7
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