lkml.org 
[lkml]   [2012]   [Oct]   [31]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 2/4, v2] AMD64 EDAC: Add support for >255 memory controllers
On Wed, Oct 31, 2012 at 04:48:12PM +0800, Daniel J Blueman wrote:
> As the AMD64 last-level-cache ID is 16-bits and federated systems
> eg using Numascale's NumaConnect/NumaChip can have more than 255 memory
> controllers, use 16-bits to store the ID.
>
> v2: Avoid change to intlv_en variable
>
> Signed-off-by: Daniel J Blueman <daniel@numascale-asia.com>
> ---
> drivers/edac/amd64_edac.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index 18d404a..28b2005 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -942,7 +942,8 @@ static u64 get_error_address(struct mce *m)
> struct amd64_pvt *pvt;
> u64 cc6_base, tmp_addr;
> u32 tmp;
> - u8 mce_nid, intlv_en;
> + u16 mce_nid;
> + u8 intlv_en;
>
> if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
> return addr;
> @@ -1499,7 +1500,7 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
> u8 channel;
> bool high_range = false;
>
> - u8 node_id = dram_dst_node(pvt, range);
> + u16 node_id = dram_dst_node(pvt, range);

No need for that change since the field dram_dst_node returns is 3 bits
wide (see F1x4{0,4}).

--
Regards/Gruss,
Boris.


\
 
 \ /
  Last update: 2012-10-31 20:01    [W:0.044 / U:0.016 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site