Messages in this thread | | | Subject | Re: [PATCH] memcg: remove unneeded preempt_disable | From | James Bottomley <> | Date | Thu, 25 Aug 2011 11:34:34 -0700 |
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Christoph Lameter <cl@linux.com> wrote:
>On Thu, 25 Aug 2011, James Bottomley wrote: > >> >ARM seems to have these LDREX/STREX instructions for that purpose >which >> >seem to be used for generating atomic instructions without lockes. I >> >guess >> >other RISC architectures have similar means of doing it? >> >> Arm isn't really risc. Most don't. However even with ldrex/strex >you need two instructions for rmw. > >Well then what is "really risc"? RISC is an old beaten down marketing >term >AFAICT and ARM claims it too.
Reduced Instruction Set Computer. This is why we're unlikely to have complex atomic instructions: the principle of risc is that you build them up from basic ones.
James -- Sent from my Android phone with K-9 Mail. Please excuse my brevity and top posting.
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