Messages in this thread | | | Subject | Re: [PATCH 0/2] jump label: 2.6.38 updates | From | Benjamin Herrenschmidt <> | Date | Tue, 15 Feb 2011 16:20:18 -0600 |
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On Tue, 2011-02-15 at 13:27 -0800, David Miller wrote: > From: Will Simoneau <simoneau@ele.uri.edu> > Date: Tue, 15 Feb 2011 16:11:23 -0500 > > > Note how the cache and cache coherence protocol are fundamental parts of this > > operation; if these instructions simply bypassed the cache, they *could not* > > work correctly - how do you detect when the underlying memory has been > > modified? > > The issue here isn't L2 cache bypassing, it's local L1 cache bypassing. > > The chips in question aparently do not consult the local L1 cache on > "ll" instructions. > > Therefore you must only ever access such atomic data using "ll" > instructions.
Note that it's actually a reasonable design choice to not consult the L1 in these case .... as long as you invalidate it on the way. That's how current powerpcs do it afaik, they send a kill to any matching L1 line along as reading from the L2. (Of course, L1 has to be write-through for that to work).
Cheers, Ben.
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