Messages in this thread | | | Date | Wed, 14 Dec 2011 22:37:13 +0100 | From | Francois Romieu <> | Subject | Re: [PATCH 1/1] r8169.c correct MSIEnable register offset |
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Su Kang Yin <cantona@cantona.no-ip.org> : > correct MSIEnable (bit 5) register to Config1 (offset 0x52) instead of > Config2 (offset 0x53)
I wonder where the inspiration for the MSIEnable bit came from. It looks like something was confused with the Message Control word in PCI space.
Imho you can simply remove it altogether.
-- Ueimor
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