Messages in this thread | | | Date | Sat, 03 Jul 2010 13:11:13 +0300 | From | Avi Kivity <> | Subject | Re: [PATCH v2] KVM: IOAPIC: only access APIC registers one dword at a time |
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On 07/02/2010 11:00 AM, Xiao Guangrong wrote: > The IOAPIC spec says: > > When accessing these registers, accesses must be done one dword at a time. > For example, software should never access byte 2 from the Data register before > accessing bytes 0 and 1. The hardware will not attempt to recover from a bad > programming model in this case. > > So, this patch removes other width access > >
The ioapic code also implements the ia64 iosapic. I'm guessing that does support 64-bit accesses. Please check the iosapic documentation.
There might be guests that use incorrect access despite the documentation; if real hardware supports it, it should work. So we need to start with just a warning, and allow the access. Later we can drop the invalid access.
> @@ -288,6 +288,11 @@ static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, > ioapic_debug("addr %lx\n", (unsigned long)addr); > ASSERT(!(addr& 0xf)); /* check alignment */ > > + if (len != 4) { > + printk(KERN_WARNING "ioapic: wrong length %d\n", len); > + return 0; > + } > + >
Guest triggered, so needs to be rate limited.
-- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.
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