Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 21 Apr 2010 11:02:42 +0200 | Subject | Re: [PATCH 11/12] perf, x86: implement AMD IBS event configuration | From | Stephane Eranian <> |
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On Wed, Apr 21, 2010 at 10:47 AM, Robert Richter <robert.richter@amd.com> wrote: > On 20.04.10 18:05:57, Robert Richter wrote: >> > What is the problem with directly using the period here, rejecting >> > any value that is off range or with bottom 4 bits set? >> >> Yes, I will create an updated version of this patch. > > Stephane, do you think having the lower 4 bits set is worth an EINVAL? > I would rather ignore them since the accuracy is not really necessary > compared to a range lets say from 100000 cycles? Otherwise this will > make the setup of ibs much more complicated. The check could be moved > to userland and generate a waring or so.
Explain why you think it would be more complicated? If I recall there is already a function to validate the attrs: amd_pmu_hw_config(). But may be you are talking about userland setup.
Here is one argument why this might be important. Some people like to know exactly the sampling period because they use a particular value, like a prime number. You chopping off the bottom 4 bits could break this logic silently.
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