Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 21 Apr 2010 22:43:54 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH 0/5] AMD L3 cache index disable fixes for .35 |
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From: Borislav Petkov <bp@amd64.org> Date: Thu, Apr 15, 2010 at 06:40:58PM +0200
Ping.
It would be cool if we could sort out objections soon (in case there are any, of course) so that the patches can have some -tip time before the .35 merge window.
Thanks.
> From: Borislav Petkov <borislav.petkov@amd.com> > > Hi, > > this is a small patchset of fixes for L3 CID which have accumulated over > the last couple of weeks. They serve as a preparation for disabling L3 > cache indices whenever an L3 MCE triggers, has been evaluated and the > offending index thresholded and, if error rate is excessively high, > disabled. Those patches will be coming up later though. > > Patches 1,3,4 are cleanups and unifications which save us a little bit > of percpu memory in favor of dynamic allocation. Also, we have an L3 > cache descriptor per node now instead of having this information per > CPU. > > I triggered a lockdep warning in lockdep_trace_alloc() during testing > due to the fact that we may run with disabled interrupts that early > in the boot process. Therefore, I have a GFP_ATOMIC in patch 3 there > allocating the cache descriptors. I'm open for suggestions in case this > is undesired. > > Patch 2 is a fix which triggers when we run as a guest on Xen due to Xen > not exporting CPU PCI config space to the guests. > > And finally #5 is a required fix. > > The patchset is also available at > git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git l3-for-35 > > Please queue for .35, > thanks. >
-- Regards/Gruss, Boris.
-- Advanced Micro Devices, Inc. Operating Systems Research Center
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