Messages in this thread | | | Subject | Re: [PATCH 1/3] jump label: add enabled/disabled state to jump label key entries | From | Benjamin Herrenschmidt <> | Date | Fri, 26 Nov 2010 08:26:05 +1100 |
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On Fri, 2010-11-26 at 00:42 +1100, Michael Ellerman wrote: > > Ooh, nice, so the CPUs won't get all confused because you change > code > > from under their ifetch cache? > > Apparently not, at least according to the architecture.
As long as you are atomically changing one word fully aligned (remember, no variable length instructions on ppc :-) you are fine. The other CPU will see either the old or the new value, not something in between.
The dcbf/sync/icbi/isync is really only necessary on older processors. dcbf will broadcast a request to flush that line out of D, sync will wait for that to complete, icbi will broadcast an invalidate of that line out of I, sync will wait for that to have gone out and isync will locally synchronize the pipeline (toss prefetch).
Now, P5 and later have a HW snoop of I/D, so dcbf isn't useful. You need at least an isync tho to ensure prefetched stuff has been tossed or you may still execute the "old" instructions for a little while.
On P7 (I'm not sure about 5 and 6 here), additionally, they have sneaky optimisations in isync (bcs some people abuse it as a read barrier) using a scoreboard to decide what to do. In essence, that means that alone, it won't toss prefetch unless scoreboarded to do so by a previous icbi. So one icbi (regardless of how much you want to invalidate and with any address) followed by isync will do.
An interrupt will do too tho :-)
Cheers, Ben.
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