Messages in this thread | | | Date | Thu, 03 Sep 2009 20:51:44 -0700 | From | "H. Peter Anvin" <> | Subject | Re: [tip:x86/asm] x86/i386: Make sure stack-protector segment base is cache aligned |
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On 09/03/2009 08:47 PM, Tejun Heo wrote: > H. Peter Anvin wrote: >> On 09/03/2009 07:59 PM, Tejun Heo wrote: >>> Another question. Other than saving and loading an extra segment >>> register on kernel entry/exit, whether using the same or different >>> segment registers doesn't look like would make difference >>> performance-wise. If I'm interpreting the wording in the optimization >>> manual correctly, it means that each non-zero segment based memory >>> access will be costly regardless of which specific segment register is >>> in use and there's no way we can merge segment based dereferences for >>> stackprotector and percpu variables. >>> >> It's correct that it doesn't make any difference for access, only for load. > > Heh... here's a naive and hopeful plan. How about we beg gcc > developers to allow different segment register and offset in newer gcc > versions and then use the same one when building with the new gcc? > This should solve the i386 problem too. It would be the best as we > get to keep the separate segment register from the userland. Too > hopeful?
I think it's possible to set the register in more recent gcc. Doing the sane thing and having a symbol for an offset is probably worse.
I can talk to H.J. Lu about this tomorrow.
-hpa
-- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf.
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