Messages in this thread | | | Date | Tue, 22 Sep 2009 21:11:01 +0200 | From | Arjan van de Ven <> | Subject | Re: TI PCIe-PCI bridge quirks |
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On Tue, 22 Sep 2009 14:01:06 -0500 Gabe Black <gabebblack@gmail.com> wrote:
> Hi, > > The TI XIO2000A/XIO2200A PCIe-PCI bridge (VID: 104C, DID: 8231) > erroneously handles fast back-to-back transfers on its subordinate bus > segment. The behavior is seen when there are multiple devices > downstream and transfers from both devices result in a fast b2b > transfer. This confuses the PCIe-PCI bridge and results in data > corruption. > > One way to work around the buggy bridge would be to disable fast b2b > transfers on any device on the subordinate bus-segment by writing the > appropriate bits in the device's pci-configspace command register. > > Are there any suggestions on how this might be handled? Should this > be addressed in the kernel?
sounds like this is worth a PCI quirk in the kernel...
-- Arjan van de Ven Intel Open Source Technology Centre For development, discussion and tips for power savings, visit http://www.lesswatts.org
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