Messages in this thread | | | Date | Wed, 9 Dec 2009 13:37:09 -0600 | Subject | Re: [PATCH v2] calgary: Increase the maximum PHB bus number | From | Jon Mason <> |
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Thanks for fixing the comment
Acked-by: Jon Mason <jdmason@kudzu.us>
On Wed, Dec 9, 2009 at 12:40 PM, Darrick J. Wong <djwong@us.ibm.com> wrote: > Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the > limits up and provide an explanation of the requirements for each class. > > Signed-off-by: Darrick J. Wong <djwong@us.ibm.com> > Acked-by: Muli Ben-Yehuda <muli@il.ibm.com> > --- > > arch/x86/kernel/pci-calgary_64.c | 13 +++++++++---- > 1 files changed, 9 insertions(+), 4 deletions(-) > > > diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c > index e6ec8a2..4b7eb90 100644 > --- a/arch/x86/kernel/pci-calgary_64.c > +++ b/arch/x86/kernel/pci-calgary_64.c > @@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0; > #define PMR_SOFTSTOPFAULT 0x40000000 > #define PMR_HARDSTOP 0x20000000 > > -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ > -#define MAX_NUM_CHASSIS 8 /* max number of chassis */ > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ > -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) > +/* > + * The maximum PHB bus number. > + * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384 > + * x3950M2: 4 chassis, 48 PHBs per chassis = 192 > + * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256 > + * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128 > + */ > +#define MAX_PHB_BUS_NUM 384 > + > #define PHBS_PER_CALGARY 4 > > /* register offsets in Calgary's internal register space */ > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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