Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 23 Dec 2009 21:34:45 +0100 | From | alain <> | Subject | Re: [Fdutils] DMA cache consistency bug introduced in 2.6.28 |
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Pallipadi, Venkatesh wrote: > MSI interrupt being delivered to CPU 0. I cannot think of any reason why > this can break dma. We can probably try adding some dummy HPET read > after dma write, to see if that flushes things properly.
Shouldn't that be "... some dummy HPET read _before_ dma write...". In order to ensure that DMA cache is consistent _before_ dma controller reads it?
Regards,
Alain
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