Messages in this thread | | | Date | Fri, 11 Dec 2009 15:38:52 +0100 | Subject | Re: [PATCH] perf_events: improve Intel event scheduling | From | Stephane Eranian <> |
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On Fri, Dec 11, 2009 at 12:00 PM, stephane eranian <eranian@googlemail.com> wrote: >>> --- a/arch/x86/kernel/cpu/perf_event.c >>> +++ b/arch/x86/kernel/cpu/perf_event.c >> >>> @@ -68,6 +69,15 @@ struct debug_store { >>> u64 pebs_event_reset[MAX_PEBS_EVENTS]; >>> }; >>> >>> +#define BITS_TO_U64(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(u64)) >> >> Do we need this, is it realistic to expect X86_PMC_IDX_MAX to be >> anything else than 64? >> > The issue had to do with i386 mode where long are 32 bits < 64. And in > particular with the initializer .idxmsk[0] = V. In the future we may exceed > 32 registers. That means the initializer would have to change. But I guess > we have quite some ways before this case is reached. So I will revert all > of this to unsigned long. > Well, in fact we have to use u64 because you are already using register indexes > 32, e.g., for the Intel fixed counters which start at position 32. Using unsigned long would make the static initializer uglier in this case. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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