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SubjectRe: [PATCH 4/6 v3] PCI: support SR-IOV capability
Date
 > +       ctrl = pci_ari_enabled(dev) ? PCI_IOV_CTRL_ARI : 0;
> + pci_write_config_word(dev, pos + PCI_IOV_CTRL, ctrl);
> + ssleep(1);

You seem to sleep for 1 second wherever you write the IOV_CTRL
register. Why is this? Is this specified by PCI, or is it coming from
somewhere else?

- R.


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