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    Subject[patch 1/9] x86, xsave: xsave cpuid feature bits
    Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
    ---

    Index: tip-0728/arch/x86/kernel/cpu/feature_names.c
    ===================================================================
    --- tip-0728.orig/arch/x86/kernel/cpu/feature_names.c 2008-07-28 18:19:50.000000000 -0700
    +++ tip-0728/arch/x86/kernel/cpu/feature_names.c 2008-07-28 18:19:53.000000000 -0700
    @@ -46,7 +46,7 @@
    "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
    "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
    NULL, NULL, "dca", "sse4_1", "sse4_2", "x2apic", NULL, "popcnt",
    - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
    + NULL, NULL, "xsave", NULL, NULL, NULL, NULL, NULL,

    /* VIA/Cyrix/Centaur-defined */
    NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
    Index: tip-0728/include/asm-x86/cpufeature.h
    ===================================================================
    --- tip-0728.orig/include/asm-x86/cpufeature.h 2008-07-28 18:19:50.000000000 -0700
    +++ tip-0728/include/asm-x86/cpufeature.h 2008-07-28 18:19:53.000000000 -0700
    @@ -92,6 +92,7 @@
    #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
    #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
    #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
    +#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE */

    /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
    #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
    @@ -191,6 +192,7 @@
    #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
    #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
    #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
    +#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)

    #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
    # define cpu_has_invlpg 1
    --



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