Messages in this thread | | | Date | Thu, 24 Jul 2008 08:14:47 +0900 | Subject | Re: [PATCH]: PCI: GART iommu alignment fixes [v2] | From | FUJITA Tomonori <> |
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On Thu, 24 Jul 2008 00:10:33 +0200 Joerg Roedel <joro@8bytes.org> wrote:
> On Wed, Jul 23, 2008 at 07:19:43AM -0400, Prarit Bhargava wrote: > > pci_alloc_consistent/dma_alloc_coherent does not return size aligned > > addresses. > > > > >From Documentation/DMA-mapping.txt: > > > > "pci_alloc_consistent returns two values: the virtual address which you > > can use to access it from the CPU and dma_handle which you pass to the > > card. > > > > The cpu return address and the DMA bus master address are both > > guaranteed to be aligned to the smallest PAGE_SIZE order which > > is greater than or equal to the requested size. This invariant > > exists (for example) to guarantee that if you allocate a chunk > > which is smaller than or equal to 64 kilobytes, the extent of the > > buffer you receive will not cross a 64K boundary." > > Interesting. Have you experienced any problems because of that > misbehavior in the GART code? AMD IOMMU currently also violates this > requirement. I will send a patch to fix that there too.
IIRC, only PARISC and POWER IOMMUs follow the above rule. So I also wondered what problem he hit.
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