Messages in this thread | | | From | Nick Piggin <> | Subject | Re: MMIO and gcc re-ordering issue | Date | Wed, 4 Jun 2008 12:25:49 +1000 |
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On Wednesday 04 June 2008 07:44, Trent Piepho wrote: > On Tue, 3 Jun 2008, Matthew Wilcox wrote:
> > I don't understand why you keep talking about DMA. Are you talking > > about ordering between readX() and DMA? PCI proides those guarantees. > > I guess you haven't been reading the whole thread. The reason it started > was because gcc can re-order powerpc (and everyone else's too) IO accesses > vs accesses to cachable memory (but not spin-locks), which ends up only > being a problem with coherent DMA.
I don't think it is only a problem with coherent DMA.
CPU0 CPU1 mutex_lock(mutex); writel(something, DATA_REG); writel(GO, CTRL_REG); started = 1; mutex_unlock(mutex); mutex_lock(mutex); if (started) /* oops, this can reach device before GO */ writel(STOP, CTRL_REG);
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