Messages in this thread | | | From | "Rafael J. Wysocki" <> | Subject | Re: [patch 6/6] x86: add c1e aware idle function | Date | Wed, 18 Jun 2008 22:26:06 +0200 |
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On Wednesday, 18 of June 2008, Pavel Machek wrote: > On Thu 2008-06-12 10:29:00, Thomas Gleixner wrote: > > C1E on AMD machines is like C3 but without control from the OS. Up to > > now we disabled the local apic timer for those machines as it stops > > when the CPU goes into C1E. This excludes those machines from high > > resolution timers / dynamic ticks, which hurts especially the X2 based > > laptops. > > > > The current boot time C1E detection has another more serious flaw: > > some BIOSes do not enable C1E until the ACPI processor module is > > loaded. This causes systems to stop working after that point. > > > > To work nicely with C1E enabled machines we use a separate idle > > function, which checks on idle entry whether C1E was enabled in the > > Interrupt Pending Message MSR. This allows us to do timer broadcasting > > Entering idle is quite a common operation, and reading MSR is quite > slow. Is it possible to do better here? > > What happens if ACPI BIOS toggles MSR on all cpus *while* we are > entering idle? This seems inherently racy...
Yes, and that fits the picture I'm observing on the nx6325 (see the "linux-next: Tree for June 13: IO APIC breakage on HP nx6325" thread).
Thanks, Rafael
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