Messages in this thread | | | From | David Brownell <> | Subject | Re: [spi-devel-general] [PATCH 3/4] spi: Add OF binding support for SPI busses | Date | Thu, 22 May 2008 19:26:23 -0700 |
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On Wednesday 21 May 2008, Grant Likely wrote: > > spi-controller { > > #address-cells = 2; > > #size-cells = 0; > > some-device@0,f000 { reg = < 0 f000 >; } // CS 0, SPI address f000 > > some-device@1,f000 { reg = < 1 f000 >; } // CS 1, SPI address f000 > > some-device@1,ff00 { reg = < 1 ff00 >; } // CS 1, SPI address ff00 > > } > > For SPI the CS # *is* the address. :-) > > Unlike I2C, SPI doesn't impose any protocol on the data. It is all > anonymous data out, anonymous data in, a clock and a chip select.
Very true ... but then there are SPI chips which embed addressing.
I have in mind the mcp23s08 (and mcp23s17) GPIO expanders, which support up to four chips wired in parallel on a given chipselect. The devices are distinguished by how two address pins are wired; and two bits in the command byte must match them. (I think they just recycled an I2C design into the SPI world.)
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