Messages in this thread | | | Subject | Re: [PATCH] [POWERPC] Improve (in|out)_beXX() asm code | From | Benjamin Herrenschmidt <> | Date | Wed, 21 May 2008 10:01:22 -0400 |
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On Tue, 2008-05-20 at 15:55 -0700, Trent Piepho wrote: > here doesn't appear to be any barriers to use for coherent dma other than > mb() and wmb(). > > Correct me if I'm wrong, but I think the sync isn't actually _required_ (by > memory-barriers.txt's definitions), and it would be enough to use eieio, > except there is code that doesn't use mmiowb() between I/O access and > unlocking. > > So, as I understand it, the minimum needed is eieio. To provide strict > ordering w.r.t. spin locks without using mmiowb(), you need sync. To provide > strict ordering w.r.t. normal memory, you need sync and a compiler barrier. > > Right now no archs provide the last option. powerpc is currently the middle > option. I don't know if anything uses the first option, maybe alpha? I'm > almost certain x86 is the middle option (the first isn't possible, the arch > already has more ordering than that), which is probably why powerpc used that > option and not the first.
I don't have time for that now. Can you dig into the archives ? The whole thing has been discussed at lenght already.
Ben.
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