Messages in this thread | | | Date | Tue, 19 Feb 2008 23:51:23 +0900 (JST) | Subject | Re: [spi-devel-general] atmel_spi clock polarity | From | Atsushi Nemoto <> |
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On Mon, 18 Feb 2008 23:49:18 +0100, Haavard Skinnemoen <hskinnemoen@atmel.com> wrote: > > > CLK ______________________|~|___|~~~|___|~~~|___|~~~|___ > > > > ... and at T1 CPOL is changed?? That's wrong. There should > > never be a partial clock period while a chipselect is active. > > While it's inactive, sure -- no chip should care. > > ...but what I'm afraid of is that since we're using GPIO chipselects, > the controller may _think_ that no chip is selected and change the > clock polarity just before it would pull the chipselect low if we were > using automatic chipselects...
Yes. That's I suppose.
> If that's the case, it would be a bit strange if it actually helped to > initialize all the CSRn registers, but it would also offer us a nice > workaround...
I suppose the clock state of the AT91 just follows _last_ transfer. My patch (setting all CSRn.POL for next transfer) was based on that assumption.
> Atsushi, do you by any chance have debugging enabled? That would > explain the long delay from CS activation to the change of clock > polarity. Compared to printk() the DMA setup takes almost no time at > all.
No, I did not enabled debugging.
> If you can confirm that my patch helps, I think that's the one we want > in mainline.
Unfortunately I had no time to try it today. Hopefully tomorrow...
--- Atsushi Nemoto
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