Messages in this thread | | | Subject | RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part | From | David Woodhouse <> | Date | Sat, 04 Oct 2008 07:09:57 +0100 |
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On Fri, 2008-10-03 at 17:53 -0700, Yu, Fenghua wrote: > >Architecturally, I'm surprised that ia64 would need to actually do a > >cache flush. I would think the VT-d hardware would do coherent > accesses which would make the cache flush unnecessary. > > VT-d hardware supports both non cache coherency and cache coherency by > bit Coherency in Extended Capabilities Register.
But is the version without the cache coherency actually going to be _seen_ on IA64?
> Could you please point me to the doc that explicitly says that > architecturally ia64 doesn't need cache flush?
For safety, we can always make the driver just refuse to initialise on IA64 if the cache coherency bit isn't set.
-- David Woodhouse Open Source Technology Centre David.Woodhouse@intel.com Intel Corporation
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