Messages in this thread | | | Date | Fri, 31 Aug 2007 10:41:26 +0200 | From | John Sigler <> | Subject | Re: hda: set_drive_speed_status: status=0x51 { DriveReady SeekComplete Error } |
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Eric wrote:
> John Sigler wrote: > >> According to my supplier, herre is the data sheet for the DOMs: >> http://www.pqimemory.com/documents/domdata.pdf >> >> PIO mode 2 is mentioned. Even DMA seems to be supported. >> Or am I mistaken? > > Page 3 states max interface burst speed is 8.3MB/s in PIO2. I > wouldn't assume it supports DMA
The reason I suspected DMA support is because I noticed the description of DMACK- (DMA acknowledge) and DMARQ (DMA request).
> Based on the quoted media transfer rates (1.2MB/s write and 4.1MB/s > read), DMA would buy you a transfer checksum but probably not much > performance, unless your embedded application is CPU bound.
What I fear is that programmed I/O will tie up the CPU and add non-deterministic latency to my real-time apps.
Suppose that an app is waiting for an acknowledgement from a PCI device when the OS suddenly decides it is time to write 4 KB to disk. Typical write rate is quoted as 1.2 MB/s i.e. the write would require at least 3.4 ms to complete.
My fear is that the entire transfer is done in a non-preemptible critical section. In other words, my real-time app would be delayed several milliseconds, which is unacceptable.
Am I mistaken?
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