Messages in this thread | | | Date | Fri, 17 Aug 2007 15:04:48 +1000 | From | Paul Mackerras <> | Subject | Re: [PATCH 0/24] make atomic_read() behave consistently across all architectures |
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Herbert Xu writes:
> So the point here is that if you don't mind getting a stale > value from the CPU cache when doing an atomic_read, then > surely you won't mind getting a stale value from the compiler > "cache".
No, that particular argument is bogus, because there is a cache coherency protocol operating to keep the CPU cache coherent with stores from other CPUs, but there isn't any such protocol (nor should there be) for a register used as a "cache".
(Linux requires SMP systems to keep any CPU caches coherent as far as accesses by other CPUs are concerned. It doesn't support any SMP systems that are not cache-coherent as far as CPU accesses are concerned. It does support systems with non-cache-coherent DMA.)
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