lkml.org 
[lkml]   [2007]   [Jul]   [6]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: [patch 10/10] Scheduler profiling - Use immediate values
    On Fri, Jul 06, 2007 at 10:50:30AM -0700, Li, Tong N wrote:
    > > Also cache misses in this situation tend to be much more than 48
    > cycles
    > > (even an K8 with integrated memory controller with fastest DIMMs is
    > > slower than that) Mathieu probably measured an L2 miss, not a load
    ^^^^^^^

    I meant L2 cache hit of course


    > from
    > > RAM.
    > > Load from RAM can be hundreds of ns in the worst case.
    > >
    >
    > The 48 cycles sounds to me like a memory load in an unloaded system, but
    > it is quite low. I wonder how it was measured...

    I found that memory latency is difficult to measure in modern x86
    CPUs because they have very clever prefetchers that can often
    outwit benchmarks.

    Another trap on P4 is that RDTSC is actually quite slow and synchronizes
    the CPU; that can add large measurement errors.

    -Andi

    -
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to majordomo@vger.kernel.org
    More majordomo info at http://vger.kernel.org/majordomo-info.html
    Please read the FAQ at http://www.tux.org/lkml/

    \
     
     \ /
      Last update: 2007-07-06 22:07    [W:3.333 / U:0.028 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site