Messages in this thread | | | Date | Fri, 8 Jun 2007 11:25:27 -0700 | From | "Keshavamurthy, Anil S" <> | Subject | Re: [Intel-IOMMU 05/10] IOVA allocation and management routines |
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On Thu, Jun 07, 2007 at 04:34:17PM -0700, Andrew Morton wrote: > On Wed, 06 Jun 2007 11:57:03 -0700 > anil.s.keshavamurthy@intel.com wrote: > > > + > > +#define PAGE_SHIFT_4K (12) > > +#define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K) > > +#define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K) > > +#define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K) > > hm. We can't use the architecture's PAGE_SHIFT and friends here? I will see how I can get rid of this.
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