Messages in this thread | | | Date | Thu, 08 Mar 2007 14:39:15 -0800 | From | Zachary Amsden <> | Subject | Re: hardwired VMI crap |
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Ingo Molnar wrote: > * Zachary Amsden <zach@vmware.com> wrote: > > >> Ingo, either you or Thomas have vetoed every attempt we have made to >> make our code operate with clockevents. [...] >> > > this is news to me - do you have any proof of such a veto? >
Yes, your refusal to discuss any technical details when asked point blank which solution you prefer, and your continued whining and threatening to unmerge our code.
And I ask again for your feedback on which approach you think is correct:
1) Rewrite the interrupt subsystem of our hypervisor, making it incompatible with full virtualization, so that we can support an abstract interrupt controller with a "clean" interface 2) Reuse the same method that HPET, PIT and other time clients in i386 use - the global_clock_event pointer which allows you to wrest control back from the APIC and reuse the lapic_events local clockevents. 3) Create a new low level interrupt handler for the per-cpu VMI timer IRQs instead of re-using the APIC handler 4) Use the irq APIs to allocate IRQ-0 as a percpu IRQ, then change the IO-APIC code so it can know not to convert this PIC IRQ into a IO-APIC edge IRQ. 5) Disable the io-apic code entirely in paravirt mode. Rather than change it, merge a parallel copy of it into the VMI code so that we can use the 99% of the code we need, with the one bugfix for #4 above 6) Disable the apic code entirely in paravirt mode. Rather than change it, merge a parallel copy of into the VMI code so that we can use the 90% of the code we need, with changes to the LVT0 timer handling. 7) For SMP only, allocate a non-shared IO-APIC IRQ, then after the IO-APIC is initialized, magically switch this to a percpu handler and start delivering local timer interrupts via this IRQ. 8) Create a pie-in-the-sky single interrupt source, reserve an IDT vector for it (or steal the lapic timer slot), and use the irq apis to set it up to be handled as a per-cpu interrupt. This actually sounds pretty good, to me. The only problem is we will need to switch the timer IRQ from IRQ 0 to this vector when the APIC is initialized, but I think we already have all the machinery we need to handle that. 9) ???
Zach
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