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SubjectRe: [PATCH -mm 1/5] Blackfin: blackfin architecture patch update
Date
On Mon 5 Mar 2007 07:39, Paul Mundt pondered:
> On Mon, Mar 05, 2007 at 01:32:07PM +0100, Bernd Schmidt wrote:
> > Paul Mundt wrote:
> > >>+comment "Memory Optimizations"
> > >>+
> > >>+config I_ENTRY_L1
> > >>+   bool "Locate interrupt entry code in L1 Memory"
> > >>+   default y
> > >>+   help
> > >>+     If enabled interrupt entry code (STORE/RESTORE CONTEXT) is
> > >> linked +     into L1 instruction memory.(less latency)
> > >>+
> > >
> > >Wow, this is really crying out for a special linker section with
> > > slightly more intelligent relocation logic. You should flag the
> > > performance critical parts to be located in L1 memory directly with a
> > > section attribute, rather than making everything selectable. If you
> > > overflow you can simply spill in to main memory.
> >
> > This is done intentionally, because it's also possible for user code to
> > be loaded into L1 memory.  We want to give users the option to avoid
> > filling it all up with kernel code.
>
> So then why not make the userspace component of it optional and allow a
> size cap for kernel usage that's configurable if it's enabled? This degree
> of abstraction is almost worse than no abstraction.

I don't understand why you think lots of options are a bad thing??

For most embedded targets, people want/need easy knobs to turn to try and
optimise the system level performance. I would guess that SH users want to do
the same thing?

That is what this does - it is just a easy to use knob.

-Robin
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