Messages in this thread | | | Date | Tue, 27 Nov 2007 12:51:09 -0800 | From | Andrew Morton <> | Subject | Re: enable dual rng on VIA C7 |
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On Tue, 27 Nov 2007 13:50:53 -0500 Dave Jones <davej@redhat.com> wrote:
> On Tue, Nov 27, 2007 at 05:08:26PM +0100, Udo van den Heuvel wrote: > > Dave Jones wrote: > > > On Mon, Nov 26, 2007 at 06:02:39PM +0100, Udo van den Heuvel wrote: > > > > > > > I did not know we are already that far ;-) > > > > I mean: can this patch be aplied without hurting C3/C7 CPU's with just > > > > one RNG? Maybe an expert needs to test/answer? > > > > Maybe some logic needs to be applied around the extra bit? > > > > > >>From the padlock spec.. > > > > > > "SRC Bits[9:8] Noise source select (I): These bits control the two noise > > > sources on the processor that input bits to the accumulation buffers. > > > On Nehemiah processors prior to stepping 8, these bits are reserved > > > and undefined. The default RESET state is both bits = 0." > > > > > > Something like this perhaps ? > > > > Yes, I think that's a big step in the right direction! > > > > But I am no expert and cannot really judge how necessary or correct the > > implementation is w.r.t. the 'undefined' function bits for CPU's that > > lack a certain feature. > > The checks at the end of the patch for the x86_mask/model ensure > we only enable the 2nd noise source on CPUs documented to have it, > so we should be safe. > > Andrew, want to throw that in the -mm pile for a while? >
Did that, renamed to "via-rng: enable secondary noise source on CPUs where it is present".
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