Messages in this thread | | | Date | Wed, 17 Oct 2007 14:24:35 +0200 | From | Nick Piggin <> | Subject | Re: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers) |
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On Wed, Oct 17, 2007 at 02:30:32AM +0200, Mikulas Patocka wrote: > > > You already must not place any data structures into WC memory --- for > > > example, spinlocks wouldn't work there. > > > > What do you mean "already"? > > I mean "in current kernel" (I checked it in 2.6.22)
Ahh, that's not "current kernel", though ;)
4071c718555d955a35e9651f77086096ad87d498
> > If we already have drivers loading data from > > WC memory, then rmb() needs to order them, whether or not they actually > > need it. If that were prohibitively costly, then we'd introduce a new > > barrier which does not order WC memory, right? > > > > > > > wmb() also won't work on WC > > > memory, because it assumes that writes are ordered. > > > > You mean the one defined like this: > > #define wmb() asm volatile("sfence" ::: "memory") > > ? If it assumed writes are ordered, then it would just be a barrier(). > > You read wrong part of the include file. Really, it is > (2.6.22,include/asm-i386/system.h): > #ifdef CONFIG_X86_OOSTORE > #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", > X86_FEATURE_XMM) > #else > #define wmb() __asm__ __volatile__ ("": : :"memory") > #endif > > CONFIG_X86_OOSTORE is dependent on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 > --- so on Intel and AMD, it is really just barrier(). > > So drivers can't assume that wmb() works on write-combining memory.
Drivers should be able to assume that wmb() orders _everything_ (except some whacky Altix thing, which I really want to fold under wmb at some point anyway).
So I decided that old x86 semantics isn't right, and now it really is a lock op / sfence everywhere.
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