lkml.org 
[lkml]   [2006]   [Sep]   [7]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: question regarding cacheline size
Matthew Wilcox wrote:
> On Thu, Sep 07, 2006 at 02:33:25PM +0200, Arjan van de Ven wrote:
>>> So I think we should redo the PCI subsystem to set cacheline size during
>>> the buswalk rather than waiting for drivers to ask for it to be set.
>> ... while allowing for quirks for devices that go puke when this
>> register gets written ;)
>>
>> (afaik there are a few)
>
> So you want:
>
> unsigned int no_cls:1; /* Device pukes on write to Cacheline Size */
>
> in struct pci_dev?

The spec says that devices can put additional restriction on supported
cacheline size (IIRC, the example was something like power of two >= or
<= certain size) and should ignore (treat as zero) if unsupported value
is written. So, there might be need for more low level driver
involvement which knows device restrictions, but I don't know whether
such devices exist.

--
tejun
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2006-09-07 14:59    [W:0.068 / U:0.024 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site