Messages in this thread | | | From | Oliver Neukum <> | Subject | Re: Uses for memory barriers | Date | Tue, 12 Sep 2006 12:22:00 +0200 |
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Am Dienstag, 12. September 2006 11:01 schrieb David Howells: > Paul E. McKenney <paulmck@us.ibm.com> wrote: > > > 2. All stores to a given single memory location will be perceived > > as having occurred in the same order by all CPUs. > > Does that take into account a CPU combining or discarding coincident memory > operations? > > For instance, a CPU asked to issue two writes to the same location may discard > the first if it hasn't done it yet.
Does it make sense? If you do: mov #x, $a wmb mov #y, $b wmb mov #z, $a
The CPU must not discard any write. If you do
mov #x, $a mov #y, $b wmb mov #z, $a
The first store to $a is superfluous if you have only inter-CPU issues in mind.
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