lkml.org 
[lkml]   [2006]   [Sep]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: Uses for memory barriers
Date
Am Dienstag, 12. September 2006 11:01 schrieb David Howells:
> Paul E. McKenney <paulmck@us.ibm.com> wrote:
>
> > 2. All stores to a given single memory location will be perceived
> > as having occurred in the same order by all CPUs.
>
> Does that take into account a CPU combining or discarding coincident memory
> operations?
>
> For instance, a CPU asked to issue two writes to the same location may discard
> the first if it hasn't done it yet.

Does it make sense? If you do:
mov #x, $a
wmb
mov #y, $b
wmb
mov #z, $a

The CPU must not discard any write. If you do

mov #x, $a
mov #y, $b
wmb
mov #z, $a

The first store to $a is superfluous if you have only inter-CPU
issues in mind.

Regards
Oliver
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2006-09-12 19:21    [W:0.135 / U:0.268 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site