Messages in this thread | | | From | Andi Kleen <> | Subject | Re: [PATCH RFC 0/6] Implement per-processor data areas for i386. | Date | Sun, 27 Aug 2006 20:07:47 +0200 |
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> your worst case scenario would be if the segment override would make it > a "complex" instruction, so not parallel decodable. That'd mean it would > basically cost you 6 or 7 instruction slots that can't be filled... > while an and and such at least run nicely in parallel with other stuff. > I don't know which if any processors actually do this, but it's rare/new > enough that I'd not be surprised if there are some.
On AMD K7/K8 a segment register prefix is a single cycle penalty.
I couldn't find anything in the Intel optimization manuals on it, but I assume it's also not dramatic.
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