Messages in this thread | | | Date | Wed, 26 Apr 2006 15:22:52 -0700 | From | Zachary Amsden <> | Subject | Re: [PATCH] i386: PAE entries must have their low word cleared first |
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Brunner, Richard wrote: > > > Maybe the barrier is needed for other architectures, but two writes > to WB memory are not going to happen out of order and so no > barrier is needed on x86 to the best of my knowledge. >
The barrier here is just a compiler barrier - wmb on x86 is just asm volatile ("" ::: "memory"); This is needed to stop gcc reordering the stores - not because the processor does respect them.
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