Messages in this thread | | | From | Florian Weimer <> | Subject | Re: [PATCH] AMD64: fix mce_cpu_quirks typos | Date | Wed, 01 Feb 2006 20:49:58 +0100 |
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* Dave Jones:
> On Wed, Feb 01, 2006 at 08:14:56PM +0100, Florian Weimer wrote: > > The spurious MCE is TLB-related. I *think* the bit for the correct > > status code is stored at position 10 HEX, not 10 DEC > > not true. According to the BIOS writer guide, it's bit 10. > The register only defines bits up to bit 12
Okay, so why I'm still getting these MCEs?
MCE 0 CPU 0 4 northbridge TSC 91ec03f09330 ADDR 104500000 Northbridge GART error bit61 = error uncorrected TLB error 'generic transaction, level generic' STATUS a40000000005001b MCGSTATUS 0
They are supposed to be disabled by the quirks routine, aren't they? - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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