Messages in this thread | | | Subject | Re: Ordering between PCI config space writes and MMIO reads? | From | Roland Dreier <> | Date | Tue, 24 Oct 2006 14:29:47 -0700 |
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> It is good to be conservative in this area. Some AMD chipsets at least > had ordering problems with some configurations in the K7 era.
Could you expand a little? Do you mean that the arch implementation of pci_write_config_xxx() should have extra barriers, or that drivers should do belt-and-suspenders flushes to make sure config writes are really done properly?
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