Messages in this thread | | | Subject | Re: Can context switches be faster? | From | Arjan van de Ven <> | Date | Thu, 12 Oct 2006 20:37:11 +0200 |
| |
On Thu, 2006-10-12 at 14:25 -0400, John Richard Moser wrote:
Hi,
> So apparently most CPUs virtually address L1 cache and physically > address L2; but sometimes physically addressing L1 is better.. hur.
if you are interested in this I would strongly urge you to read Curt Schimmel's book (UNIX(R) Systems for Modern Architectures: Symmetric Multiprocessing and Caching for Kernel Programmers); it explains this and related materials really really well.
> - Does the current code act on these behaviors, or just flush all > cache regardless?
the cache flushing is a per architecture property. On x86, the cache flushing isn't needed; but a TLB flush is. Depending on your hardware that can be expensive as well.
Greetings, Arjan van de Ven
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |