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SubjectRe: [Discuss][i386] Platform SMIs and their interferance with tsc based delay calibration
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Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> writes:
> +
> + /*
> + * If the upper limit and lower limit of the tsc_rate is more than
> + * 12.5% apart.
> + */
> + if (pre_start == 0 || pre_end == 0 ||
> + (tsc_rate_max - tsc_rate_min) > (tsc_rate_max >> 3)) {
> + printk(KERN_WARNING "TSC calibration may not be precise. "
> + "Too many SMIs? "
> + "Consider running with \"lpj=\" boot option\n");
> + return 0;
> + }

I think it would be better to rerun it a few times automatically
before giving up. This way it would hopefully work transparently but slower
for most users. The message is too obscure too to be usable and needs
more explanation.

And also in case the platforms in questions support EM64T
x86-64 would need to be changed too :)

-Andi
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