Messages in this thread | ![/](/images/icornerl.gif) | | From | (H. Peter Anvin) | Subject | Re: [PATCH] x86 bitops.h commentary on instruction reordering | Date | Fri, 6 Aug 2004 22:33:07 +0000 (UTC) |
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Followup to: <20040806170931.GA21683@logos.cnet> By author: Marcelo Tosatti <marcelo.tosatti@cyclades.com> In newsgroup: linux.dev.kernel > > > > > >Yes correct. *mb() usually imply barrier(). > > > > > >About the flush, each architecture defines its own instruction for doing > > >so, > > > PowerPC has "sync" and "isync" instructions (to flush the whole cache > > > and instruction cache respectively), MIPS has "sync" and so on.. > > > > So, there is no platform independent way for doing that in the kernel? > > Not really. x86 doesnt have such an instruction. >
Actually it does (sfence, lfence, mfence); they only apply to SSE loads and stores since all other x86 operations are guaranteed to be strictly ordered.
-hpa
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