Messages in this thread | | | Date | Tue, 13 Apr 2004 09:36:13 +0100 | From | Andy Whitcroft <> | Subject | Re: PAT support |
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--On 12 April 2004 17:29 -0500 Terence Ripperda <tripperda@nvidia.com> wrote:
> quite a while back, I sent out email about adding Page Attribute Table > support to the kernel (http://www.ker > neltraffic.org/kernel-traffic/kt20030616_219.html#3).
> this current patch includes the original PAT support and the new cachemap > mechanism. note that the cachemap mechanism does not actually change any > caching attributes, it only keeps track of the attributes and tests > regions. I think the end idea would be that drivers would use the normal > ioremap/change_page_attr/remap_page_range mechanisms like they already > do, and these mechanisms would in turn use cachemap to make sure there's > no conflicts. I'm completely open to how any specific details should > work, and any changes needed to be made.
Yeah, I've experemented recently with PAT too. Not had a chance to look at the code in any specifics. But I did notice there appear to be no notes or warnings on the issues of using PAT based mappings. Cirtainly there are some _very_ onerus restrictions which I have personally tested and found to be true :(. Perhaps we could get some big fat warning style comments.
Cirtainly the documentation is _very_ specific about this limitation, I think I saw this being implmented in the code.
+ * According to the INTEL documentation it is the systems responsibility + * to ensure that the PAT registers are kept in agreement on all processors + * in a system. Changing these registers must occu in a manner which + * maintains the consistency of the processor caches and translation + * lookaside buggers (TLB).
Also, I have confirmed that if you have any Intel processors which do not have the SS (Self Snoop) capability, you cannot have two independent mappings to a page with different cache attributes. I have been hit by this and you get stale data returned from the cache.
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