Messages in this thread | | | Date | Sun, 7 Mar 2004 22:18:02 -0800 | From | Grant Grundler <> | Subject | Re: [linux-usb-devel] Re: serious 2.6 bug in USB subsystem? |
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On Sat, Mar 06, 2004 at 08:37:43AM -0800, David Brownell wrote: > DMA-coherent memory is defined as "memory for which a write by either > the device or the processor can immediately be read by the processor > or device without having to worry about caching effects."
The use of "immediate" here means no other sync function needs to be called to access the data - ie don't need to call pci_sync_single().
In general, the accesses are ordered following PCI ordering rules. But every architecture (including x86) has issues with "inflight" DMA. Line based Interrupts are delivered on a different path than DMA and thus ordering can't be enforced. For example, the code around the following comment in drivers/net/tg3.c: /* * Flush PCI write. This also guarantees that our * status block has been flushed to host memory. */
> `Such a > write-buffering mechanism is clearly a type of (write-)caching effect,
No - the data is still in flight and in some deterministic time frame will become visible to the CPU. Calling it a "caching effect" confuses the issues even worse.
> and readl() would be a kind of dma_rmb(), if you will.
Yes, that's correct - but it's orthogonal to "cache coherent".
> I suspect the docs are wrong about what dma-coherent means.
Not "wrong", just misunderstood. ;^)
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