Messages in this thread | | | Subject | Re: page fault scalability patch V12 [0/7]: Overview and performance tests | From | Benjamin Herrenschmidt <> | Date | Thu, 02 Dec 2004 22:16:24 +1100 |
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On Thu, 2004-12-02 at 02:11 -0500, Jeff Garzik wrote: > Benjamin Herrenschmidt wrote: > > They may not end up in order if they are stores (the stores to the > > taskfile may be out of order vs; the loads/stores to/from the data > > register) unless you have a spinlock protecting both or a full sync (on > > ppc), but then, I don't know the ordering things on x86_64. This could > > certainly be a problem on ppc & ppc64 too. > > > Is synchronization beyond in[bwl] needed, do you think?
Yes, when potentially hop'ing between CPUs, definitely.
> This specific problem is only on Intel ICHx AFAICS, which is PIO not > MMIO and x86-only. I presumed insw() by its very nature already has > synchronization, but perhaps not...
Hrm... on "pure" x86, I would expect so at the HW level, not sure about x86_64... but there would be definitely an issue on ppc with your scheme. You need at least a full barrier before you trigger the workqueue. That may not be the problem you are facing now, but it would become one.
Ben.
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