Messages in this thread | | | Date | Sun, 14 Nov 2004 13:51:59 +0100 | From | Ingo Molnar <> | Subject | Re: [patch] Real-Time Preemption, -RT-2.6.10-rc1-mm3-V0.7.25-1 |
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* Shane Shrybman <shrybman@aei.ca> wrote:
> -#define IOAPIC_POSTFLUSH > +//#define IOAPIC_POSTFLUSH
> -#if defined(CONFIG_PREEMPT_HARDIRQS) && defined(CONFIG_SMP) > +#if defined(CONFIG_PREEMPT_HARDIRQS)
unfortunately the POST-flush is still needed. Without it i can see lots of spurious interrupts on SMP systems. (most likely caused by the ACK reaching the IO-APIC _before_ the mask-the-irq PCI-space write [which gets delayed in the chipset due to write optimizations], so the IO-APIC still thinks that the IRQ is enabled and for level-triggered IRQs this means that another interrupt is sent to the CPU.)
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