Messages in this thread | ![/](/images/icornerl.gif) | | Date | Fri, 5 Sep 2003 00:40:18 +0100 | From | Jamie Lokier <> | Subject | Re: [PATCH] fix remap of shared read only mappings |
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James Bottomley wrote: > I think you may misunderstand what I mean by coherence: Our problem is > the VIVT processor caches. Once one mapper does an msync, that data > must be visible to all the other mappers, so at that point we have to > flush the cache lines of all the other mappers. On PA, we only need to > flush one correctly aligned address to get the VIVT cache to flush all > the others. However, the kernel page cache usually holds an unaligned > reference so we need to do the extra aligned flush when this data > changes. If we didn't do the alignment, we'd need to flush every > virtual address in the current CPU translation for that page.
Ok, I understand why you want matching alignments now. :) (So that MS_INVALIDATE doesn't have to do anything).
> If you mean PROT_SEM requires immediate coherence without an msync, then > those semantics would be very tricky to achieve on parisc since we'd > need the kernel virtual address of the page in the page cache correctly > aligned as well.
Linux hasn't ever done anything useful with PROT_SEM. As far as I know, on some other systems PROT_SEM has meant that you mark pages uncacheable or similar, but only on systems where that is needed to implement IPC through the shared memory. For some definition IPC.
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