Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 25 Mar 2003 18:28:37 -0800 | From | george anzinger <> | Subject | Re: System time warping around real time problem - please help |
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Alan Cox wrote: > On Tue, 2003-03-25 at 22:55, Fionn Behrens wrote: > >>>This all sounds very much like the TSCs are drifting WRT each other. >>>Is it possible that you have some power management code (or hardware) >>>that is slowing one cpu and not the other? >> >>Well, I still don't really know what TSCs actually are (or what TSC >>stands for).
Stands for Time Stamp Counter. It is a special cpu register that basically counts cpu cycles. Some times (incorrectly me thinks) it is affected by power management code which slows the cpu by changing the cpu frequency. >> >>The only suspect in that case would be the amd76x_pm.o kernel module >>which I am admittedly using. It saves about 90Watts of power when the >>machine is idle... > > > If you are using amd76x_pm boot with "notsc", ditto for that matter > on dual athlons with APM or ACPI in some cases. In fact I wish people > would stop using the tsc for clock timing altogether. It simply doesn't > work on a lot of modern systems > I agree, however, what is really needed is not available in x86 machines, i.e. a cpu register that has a fixed and stable count rate. An I/O register is second best because of the long time it takes to read it. > >
-- George Anzinger george@mvista.com High-res-timers: http://sourceforge.net/projects/high-res-timers/ Preemption patch: http://www.kernel.org/pub/linux/kernel/people/rml
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