Messages in this thread | | | Date | Wed, 19 Mar 2003 17:01:06 +0000 | From | Dave Jones <> | Subject | Re: L2 cache detection in Celeron 2GHz (P4 based) |
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On Wed, Mar 19, 2003 at 05:53:13PM +0100, Paul Rolland wrote:
> > > You can also add that the L1 detection doesn't seem to be correct > > > either : > > > 0K Instruction cache, and 8K data cache for L1... This is not much > > > for instruction, it seems it should be 12K... > > > > That should be fixed in recent 2.4s (and not-so-recent 2.5s). > > What version are you seeing this problem on? > > Quite a recent one : 2.4.20.
Fixed as of 2.4.21pre1. The fix went in on 2nd December, and pre1 was tagged as of the 10th December.
Dave
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