Messages in this thread | | | Date | Tue, 21 Oct 2003 19:55:45 +0200 | Subject | Re: [PATCH] 1/3 Dynamic cpufreq governor and updates to ACPI P-state driver | From | Ducrot Bruno <> |
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On Tue, Oct 21, 2003 at 10:15:31AM -0700, Pallipadi, Venkatesh wrote: > > > -----Original Message----- > > From: Ducrot Bruno [mailto:ducrot@poupinou.org]
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> > Your do not handle correctly > > other processors > > than Intel. > > I am sorry. I do not understand this comment. > - Major part of Patch 1 is adding SMP awareness, which has > nothing specific to Intel at all. > - A part of patch 1 adds MSR based transition capability. > This is based on ACPI spec.
Could you tell me where you find in ACPI spec. that FfixedHW means always MSR? That not true for C-states definitions via _CST for example (the first entry being always an FFixedHW, because it is C1 and will be the single asm instruction: 'hlt'). Look 2.0b page 228.
> It will work any processor > that is ACPI compatible and again there are no specific > checks for Intel here. >
On a K7 with powernow for example, perf_ctrl and perf_data will be MSR 0 with your patch, that do not make sence. Even if you know the correct MSRs, the values for 'control' and 'status' in _PSS packages will be only bit-fields, and they can *not* be written nor read directly to the (correct) MSRs (again for K7 powernow).
This is because the FfixedHW is only an indication that a CPU specific 'feature' (even though already somehow defined in ACPI like P-state, C-state, etc.) have to be handled by the OS in a non-acpi driver, as per ACPI spec, and that will be dependant of the CPU.
-- Ducrot Bruno
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