Messages in this thread | | | Date | Mon, 20 Jan 2003 18:24:07 +0100 (CET) | From | Ingo Molnar <> | Subject | Re: [patch] sched-2.5.59-A2 |
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On Mon, 20 Jan 2003, Martin J. Bligh wrote:
> Do you have that code working already (presumably needs locking > changes)? I seem to recall something like that existing already, but I > don't recall if it was ever fully working or not ...
yes, i have a HT testbox and working code:
http://lwn.net/Articles/8553/
the patch is rather old, i'll update it to 2.5.59.
> I think the large PPC64 boxes have multilevel NUMA as well - two real > phys cores on one die, sharing some cache (L2 but not L1? Anton?). And > SGI have multilevel nodes too I think ... so we'll still need multilevel > NUMA at some point ... but maybe not right now.
Intel's HT is the cleanest case: pure logical cores, which clearly need special handling. Whether the other SMT solutions want to be handled via the logical-cores code or via another level of NUMA-balancing code, depends on benchmarking results i suspect. It will be one more flexibility that system maintainers will have, it's all set up via the sched_map_runqueue(cpu1, cpu2) boot-time call that 'merges' a CPU's runqueue into another CPU's runqueue. It's basically the 0th level of balancing, which will be fundamentally different. The other levels of balancing are (or should be) similar to each other - only differing in weight of balancing, not differing in the actual algorithm.
Ingo
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